Digital communications systems and digital storage systems (e.g., hard disk drives) are similar from the perspective of extracting the original (transmitted or stored) bits from the received signal or from the readback signal. In the case of communication channels, the digital information is transferred from one location to another location, but at the same time (perhaps with a small transmission delay), whereas in storage channels, the information is transferred from one time to a later time, but at the same location. The goal in both cases is to retrieve the original bits as accurately as possible in the presence of impairments such as noise and inter-symbol interference (ISI). Data detectors are used to detect the retrieved bits and determine whether each bit corresponds to a binary 1 or to a binary 0.
A recurring problem with existing data detectors is that they generally consume a large amount of power to achieve adequate performance, which, in turn, generates a large amount of heat. Typically, the chip package that contains the data detector is not designed to handle the excess heat caused by the large amount of power consumed. Although standard data detectors that consume less power exist, they generally sacrifice performance in order to save power.
One approach that minimizes power consumption without sacrificing performance involves using a composite data detector. A composite detector is a data detector that combines a first, relatively small data detector, and a second, relatively large and more accurate data detector. However, known composite detectors have several drawbacks, including poor efficiency. For example, one known composite detector has a smaller detector that runs continuously for an entire read event and then triggers a larger, and more accurate detector, which starts in an unknown state and has a fixed runtime of a minimum of 60 cycles after being triggered by the smaller detector. The minimum runtime of the larger detector causes it to run more often than necessary, which wastes power. Moreover, the larger detector is initiated based on path metric differences, which may not always be accurate. In the case where the larger detector is a parity-doubled Viterbi detector, no provision is made to resynchronize the larger detector in the correct parity state, which results in errors.
Accordingly, it would be desirable to provide a composite data detector that consumes a relatively small amount of power compared to known composite data detectors and that operates with greater accuracy than known composite data detectors.